// ******************************************************************************
// Copyright     :  Copyright (C) 2019, Hisilicon Technologies Co. Ltd.
// File name     :  esch_reg_offset.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :  2018/12/11
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V5.1
// History       :  xxx 2019/12/11 20:09:31 Create file
// ******************************************************************************

#ifndef ESCH_REG_OFFSET_H
#define ESCH_REG_OFFSET_H

/* ESCH_TOP_CSR Base address of Module's Register */
#define CSR_ESCH_TOP_CSR_BASE (0xB000)

/* **************************************************************************** */
/*                      ESCH_TOP_CSR Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_0_REG (CSR_ESCH_TOP_CSR_BASE + 0x0)   /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_1_REG (CSR_ESCH_TOP_CSR_BASE + 0x4)   /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_2_REG (CSR_ESCH_TOP_CSR_BASE + 0x8)   /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_3_REG (CSR_ESCH_TOP_CSR_BASE + 0xC)   /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_4_REG (CSR_ESCH_TOP_CSR_BASE + 0x10)  /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_5_REG (CSR_ESCH_TOP_CSR_BASE + 0x14)  /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_6_REG (CSR_ESCH_TOP_CSR_BASE + 0x18)  /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_7_REG (CSR_ESCH_TOP_CSR_BASE + 0x1C)  /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_8_REG (CSR_ESCH_TOP_CSR_BASE + 0x20)  /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_9_REG (CSR_ESCH_TOP_CSR_BASE + 0x24)  /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_10_REG (CSR_ESCH_TOP_CSR_BASE + 0x28) /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_11_REG (CSR_ESCH_TOP_CSR_BASE + 0x2C) /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_12_REG (CSR_ESCH_TOP_CSR_BASE + 0x30) /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_13_REG (CSR_ESCH_TOP_CSR_BASE + 0x34) /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_14_REG (CSR_ESCH_TOP_CSR_BASE + 0x38) /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_15_REG (CSR_ESCH_TOP_CSR_BASE + 0x3C) /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_16_REG (CSR_ESCH_TOP_CSR_BASE + 0x40) /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_17_REG (CSR_ESCH_TOP_CSR_BASE + 0x44) /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_18_REG (CSR_ESCH_TOP_CSR_BASE + 0x48) /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_19_REG (CSR_ESCH_TOP_CSR_BASE + 0x4C) /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_20_REG (CSR_ESCH_TOP_CSR_BASE + 0x50) /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_21_REG (CSR_ESCH_TOP_CSR_BASE + 0x54) /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_22_REG (CSR_ESCH_TOP_CSR_BASE + 0x58) /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_23_REG (CSR_ESCH_TOP_CSR_BASE + 0x5C) /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_24_REG (CSR_ESCH_TOP_CSR_BASE + 0x60) /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_25_REG (CSR_ESCH_TOP_CSR_BASE + 0x64) /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_26_REG (CSR_ESCH_TOP_CSR_BASE + 0x68) /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_27_REG (CSR_ESCH_TOP_CSR_BASE + 0x6C) /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_28_REG (CSR_ESCH_TOP_CSR_BASE + 0x70) /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_29_REG (CSR_ESCH_TOP_CSR_BASE + 0x74) /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_30_REG (CSR_ESCH_TOP_CSR_BASE + 0x78) /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_31_REG (CSR_ESCH_TOP_CSR_BASE + 0x7C) /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_32_REG (CSR_ESCH_TOP_CSR_BASE + 0x80) /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_33_REG (CSR_ESCH_TOP_CSR_BASE + 0x84) /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_34_REG (CSR_ESCH_TOP_CSR_BASE + 0x88) /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_35_REG (CSR_ESCH_TOP_CSR_BASE + 0x8C) /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_36_REG (CSR_ESCH_TOP_CSR_BASE + 0x90) /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_37_REG (CSR_ESCH_TOP_CSR_BASE + 0x94) /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_38_REG (CSR_ESCH_TOP_CSR_BASE + 0x98) /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_39_REG (CSR_ESCH_TOP_CSR_BASE + 0x9C) /* COS to CPI CH MAP */
#define CSR_ESCH_TOP_CSR_ESCH_MEM_CFG_OK_REG (CSR_ESCH_TOP_CSR_BASE + 0xA0)    /* ESCH使能配置 */
#define CSR_ESCH_TOP_CSR_ESCH_PPOP_BP_CFG_REG (CSR_ESCH_TOP_CSR_BASE + 0xA4)   /* DFX CFG */
#define CSR_ESCH_TOP_CSR_ESCH_PPOP_BP_ST_REG (CSR_ESCH_TOP_CSR_BASE + 0xA8)
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_0_REG (CSR_ESCH_TOP_CSR_BASE + 0x100)    /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_1_REG (CSR_ESCH_TOP_CSR_BASE + 0x104)    /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_2_REG (CSR_ESCH_TOP_CSR_BASE + 0x108)    /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_3_REG (CSR_ESCH_TOP_CSR_BASE + 0x10C)    /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_4_REG (CSR_ESCH_TOP_CSR_BASE + 0x110)    /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_5_REG (CSR_ESCH_TOP_CSR_BASE + 0x114)    /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_6_REG (CSR_ESCH_TOP_CSR_BASE + 0x118)    /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_7_REG (CSR_ESCH_TOP_CSR_BASE + 0x11C)    /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_8_REG (CSR_ESCH_TOP_CSR_BASE + 0x120)    /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_9_REG (CSR_ESCH_TOP_CSR_BASE + 0x124)    /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_10_REG (CSR_ESCH_TOP_CSR_BASE + 0x128)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_11_REG (CSR_ESCH_TOP_CSR_BASE + 0x12C)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_12_REG (CSR_ESCH_TOP_CSR_BASE + 0x130)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_13_REG (CSR_ESCH_TOP_CSR_BASE + 0x134)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_14_REG (CSR_ESCH_TOP_CSR_BASE + 0x138)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_15_REG (CSR_ESCH_TOP_CSR_BASE + 0x13C)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_16_REG (CSR_ESCH_TOP_CSR_BASE + 0x140)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_17_REG (CSR_ESCH_TOP_CSR_BASE + 0x144)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_18_REG (CSR_ESCH_TOP_CSR_BASE + 0x148)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_19_REG (CSR_ESCH_TOP_CSR_BASE + 0x14C)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_20_REG (CSR_ESCH_TOP_CSR_BASE + 0x150)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_21_REG (CSR_ESCH_TOP_CSR_BASE + 0x154)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_22_REG (CSR_ESCH_TOP_CSR_BASE + 0x158)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_23_REG (CSR_ESCH_TOP_CSR_BASE + 0x15C)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_24_REG (CSR_ESCH_TOP_CSR_BASE + 0x160)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_25_REG (CSR_ESCH_TOP_CSR_BASE + 0x164)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_26_REG (CSR_ESCH_TOP_CSR_BASE + 0x168)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_27_REG (CSR_ESCH_TOP_CSR_BASE + 0x16C)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_28_REG (CSR_ESCH_TOP_CSR_BASE + 0x170)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_29_REG (CSR_ESCH_TOP_CSR_BASE + 0x174)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_30_REG (CSR_ESCH_TOP_CSR_BASE + 0x178)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_31_REG (CSR_ESCH_TOP_CSR_BASE + 0x17C)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_32_REG (CSR_ESCH_TOP_CSR_BASE + 0x180)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_33_REG (CSR_ESCH_TOP_CSR_BASE + 0x184)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_34_REG (CSR_ESCH_TOP_CSR_BASE + 0x188)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_35_REG (CSR_ESCH_TOP_CSR_BASE + 0x18C)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_36_REG (CSR_ESCH_TOP_CSR_BASE + 0x190)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_37_REG (CSR_ESCH_TOP_CSR_BASE + 0x194)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_38_REG (CSR_ESCH_TOP_CSR_BASE + 0x198)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_39_REG (CSR_ESCH_TOP_CSR_BASE + 0x19C)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_40_REG (CSR_ESCH_TOP_CSR_BASE + 0x1A0)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_41_REG (CSR_ESCH_TOP_CSR_BASE + 0x1A4)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_42_REG (CSR_ESCH_TOP_CSR_BASE + 0x1A8)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_43_REG (CSR_ESCH_TOP_CSR_BASE + 0x1AC)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_44_REG (CSR_ESCH_TOP_CSR_BASE + 0x1B0)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_45_REG (CSR_ESCH_TOP_CSR_BASE + 0x1B4)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_46_REG (CSR_ESCH_TOP_CSR_BASE + 0x1B8)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_47_REG (CSR_ESCH_TOP_CSR_BASE + 0x1BC)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_48_REG (CSR_ESCH_TOP_CSR_BASE + 0x1C0)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_49_REG (CSR_ESCH_TOP_CSR_BASE + 0x1C4)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_50_REG (CSR_ESCH_TOP_CSR_BASE + 0x1C8)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_51_REG (CSR_ESCH_TOP_CSR_BASE + 0x1CC)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_52_REG (CSR_ESCH_TOP_CSR_BASE + 0x1D0)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_53_REG (CSR_ESCH_TOP_CSR_BASE + 0x1D4)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_54_REG (CSR_ESCH_TOP_CSR_BASE + 0x1D8)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_55_REG (CSR_ESCH_TOP_CSR_BASE + 0x1DC)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_56_REG (CSR_ESCH_TOP_CSR_BASE + 0x1E0)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_57_REG (CSR_ESCH_TOP_CSR_BASE + 0x1E4)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_58_REG (CSR_ESCH_TOP_CSR_BASE + 0x1E8)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_59_REG (CSR_ESCH_TOP_CSR_BASE + 0x1EC)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_60_REG (CSR_ESCH_TOP_CSR_BASE + 0x1F0)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_61_REG (CSR_ESCH_TOP_CSR_BASE + 0x1F4)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_62_REG (CSR_ESCH_TOP_CSR_BASE + 0x1F8)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_63_REG (CSR_ESCH_TOP_CSR_BASE + 0x1FC)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_64_REG (CSR_ESCH_TOP_CSR_BASE + 0x200)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_65_REG (CSR_ESCH_TOP_CSR_BASE + 0x204)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_66_REG (CSR_ESCH_TOP_CSR_BASE + 0x208)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_67_REG (CSR_ESCH_TOP_CSR_BASE + 0x20C)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_68_REG (CSR_ESCH_TOP_CSR_BASE + 0x210)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_69_REG (CSR_ESCH_TOP_CSR_BASE + 0x214)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_70_REG (CSR_ESCH_TOP_CSR_BASE + 0x218)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_71_REG (CSR_ESCH_TOP_CSR_BASE + 0x21C)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_72_REG (CSR_ESCH_TOP_CSR_BASE + 0x220)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_73_REG (CSR_ESCH_TOP_CSR_BASE + 0x224)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_74_REG (CSR_ESCH_TOP_CSR_BASE + 0x228)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_75_REG (CSR_ESCH_TOP_CSR_BASE + 0x22C)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_76_REG (CSR_ESCH_TOP_CSR_BASE + 0x230)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_77_REG (CSR_ESCH_TOP_CSR_BASE + 0x234)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_78_REG (CSR_ESCH_TOP_CSR_BASE + 0x238)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_79_REG (CSR_ESCH_TOP_CSR_BASE + 0x23C)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_80_REG (CSR_ESCH_TOP_CSR_BASE + 0x240)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_81_REG (CSR_ESCH_TOP_CSR_BASE + 0x244)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_82_REG (CSR_ESCH_TOP_CSR_BASE + 0x248)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_83_REG (CSR_ESCH_TOP_CSR_BASE + 0x24C)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_84_REG (CSR_ESCH_TOP_CSR_BASE + 0x250)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_85_REG (CSR_ESCH_TOP_CSR_BASE + 0x254)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_86_REG (CSR_ESCH_TOP_CSR_BASE + 0x258)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_87_REG (CSR_ESCH_TOP_CSR_BASE + 0x25C)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_88_REG (CSR_ESCH_TOP_CSR_BASE + 0x260)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_89_REG (CSR_ESCH_TOP_CSR_BASE + 0x264)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_90_REG (CSR_ESCH_TOP_CSR_BASE + 0x268)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_91_REG (CSR_ESCH_TOP_CSR_BASE + 0x26C)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_92_REG (CSR_ESCH_TOP_CSR_BASE + 0x270)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_93_REG (CSR_ESCH_TOP_CSR_BASE + 0x274)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_94_REG (CSR_ESCH_TOP_CSR_BASE + 0x278)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_95_REG (CSR_ESCH_TOP_CSR_BASE + 0x27C)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_96_REG (CSR_ESCH_TOP_CSR_BASE + 0x280)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_97_REG (CSR_ESCH_TOP_CSR_BASE + 0x284)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_98_REG (CSR_ESCH_TOP_CSR_BASE + 0x288)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_99_REG (CSR_ESCH_TOP_CSR_BASE + 0x28C)   /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_100_REG (CSR_ESCH_TOP_CSR_BASE + 0x290)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_101_REG (CSR_ESCH_TOP_CSR_BASE + 0x294)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_102_REG (CSR_ESCH_TOP_CSR_BASE + 0x298)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_103_REG (CSR_ESCH_TOP_CSR_BASE + 0x29C)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_104_REG (CSR_ESCH_TOP_CSR_BASE + 0x2A0)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_105_REG (CSR_ESCH_TOP_CSR_BASE + 0x2A4)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_106_REG (CSR_ESCH_TOP_CSR_BASE + 0x2A8)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_107_REG (CSR_ESCH_TOP_CSR_BASE + 0x2AC)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_108_REG (CSR_ESCH_TOP_CSR_BASE + 0x2B0)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_109_REG (CSR_ESCH_TOP_CSR_BASE + 0x2B4)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_110_REG (CSR_ESCH_TOP_CSR_BASE + 0x2B8)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_111_REG (CSR_ESCH_TOP_CSR_BASE + 0x2BC)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_112_REG (CSR_ESCH_TOP_CSR_BASE + 0x2C0)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_113_REG (CSR_ESCH_TOP_CSR_BASE + 0x2C4)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_114_REG (CSR_ESCH_TOP_CSR_BASE + 0x2C8)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_115_REG (CSR_ESCH_TOP_CSR_BASE + 0x2CC)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_116_REG (CSR_ESCH_TOP_CSR_BASE + 0x2D0)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_117_REG (CSR_ESCH_TOP_CSR_BASE + 0x2D4)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_118_REG (CSR_ESCH_TOP_CSR_BASE + 0x2D8)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_119_REG (CSR_ESCH_TOP_CSR_BASE + 0x2DC)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_120_REG (CSR_ESCH_TOP_CSR_BASE + 0x2E0)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_121_REG (CSR_ESCH_TOP_CSR_BASE + 0x2E4)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_122_REG (CSR_ESCH_TOP_CSR_BASE + 0x2E8)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_123_REG (CSR_ESCH_TOP_CSR_BASE + 0x2EC)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_124_REG (CSR_ESCH_TOP_CSR_BASE + 0x2F0)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_125_REG (CSR_ESCH_TOP_CSR_BASE + 0x2F4)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_126_REG (CSR_ESCH_TOP_CSR_BASE + 0x2F8)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_127_REG (CSR_ESCH_TOP_CSR_BASE + 0x2FC)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_128_REG (CSR_ESCH_TOP_CSR_BASE + 0x300)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_129_REG (CSR_ESCH_TOP_CSR_BASE + 0x304)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_130_REG (CSR_ESCH_TOP_CSR_BASE + 0x308)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_131_REG (CSR_ESCH_TOP_CSR_BASE + 0x30C)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_132_REG (CSR_ESCH_TOP_CSR_BASE + 0x310)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_133_REG (CSR_ESCH_TOP_CSR_BASE + 0x314)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_134_REG (CSR_ESCH_TOP_CSR_BASE + 0x318)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_135_REG (CSR_ESCH_TOP_CSR_BASE + 0x31C)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_136_REG (CSR_ESCH_TOP_CSR_BASE + 0x320)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_137_REG (CSR_ESCH_TOP_CSR_BASE + 0x324)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_138_REG (CSR_ESCH_TOP_CSR_BASE + 0x328)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_139_REG (CSR_ESCH_TOP_CSR_BASE + 0x32C)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_140_REG (CSR_ESCH_TOP_CSR_BASE + 0x330)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_141_REG (CSR_ESCH_TOP_CSR_BASE + 0x334)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_142_REG (CSR_ESCH_TOP_CSR_BASE + 0x338)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_143_REG (CSR_ESCH_TOP_CSR_BASE + 0x33C)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_144_REG (CSR_ESCH_TOP_CSR_BASE + 0x340)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_145_REG (CSR_ESCH_TOP_CSR_BASE + 0x344)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_146_REG (CSR_ESCH_TOP_CSR_BASE + 0x348)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_147_REG (CSR_ESCH_TOP_CSR_BASE + 0x34C)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_148_REG (CSR_ESCH_TOP_CSR_BASE + 0x350)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_149_REG (CSR_ESCH_TOP_CSR_BASE + 0x354)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_150_REG (CSR_ESCH_TOP_CSR_BASE + 0x358)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_151_REG (CSR_ESCH_TOP_CSR_BASE + 0x35C)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_152_REG (CSR_ESCH_TOP_CSR_BASE + 0x360)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_153_REG (CSR_ESCH_TOP_CSR_BASE + 0x364)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_154_REG (CSR_ESCH_TOP_CSR_BASE + 0x368)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_155_REG (CSR_ESCH_TOP_CSR_BASE + 0x36C)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_156_REG (CSR_ESCH_TOP_CSR_BASE + 0x370)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_157_REG (CSR_ESCH_TOP_CSR_BASE + 0x374)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_158_REG (CSR_ESCH_TOP_CSR_BASE + 0x378)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_159_REG (CSR_ESCH_TOP_CSR_BASE + 0x37C)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_160_REG (CSR_ESCH_TOP_CSR_BASE + 0x380)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_161_REG (CSR_ESCH_TOP_CSR_BASE + 0x384)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_162_REG (CSR_ESCH_TOP_CSR_BASE + 0x388)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_163_REG (CSR_ESCH_TOP_CSR_BASE + 0x38C)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_164_REG (CSR_ESCH_TOP_CSR_BASE + 0x390)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_165_REG (CSR_ESCH_TOP_CSR_BASE + 0x394)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_166_REG (CSR_ESCH_TOP_CSR_BASE + 0x398)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_167_REG (CSR_ESCH_TOP_CSR_BASE + 0x39C)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_168_REG (CSR_ESCH_TOP_CSR_BASE + 0x3A0)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_169_REG (CSR_ESCH_TOP_CSR_BASE + 0x3A4)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_170_REG (CSR_ESCH_TOP_CSR_BASE + 0x3A8)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_171_REG (CSR_ESCH_TOP_CSR_BASE + 0x3AC)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_172_REG (CSR_ESCH_TOP_CSR_BASE + 0x3B0)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_173_REG (CSR_ESCH_TOP_CSR_BASE + 0x3B4)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_174_REG (CSR_ESCH_TOP_CSR_BASE + 0x3B8)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_175_REG (CSR_ESCH_TOP_CSR_BASE + 0x3BC)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_176_REG (CSR_ESCH_TOP_CSR_BASE + 0x3C0)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_177_REG (CSR_ESCH_TOP_CSR_BASE + 0x3C4)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_178_REG (CSR_ESCH_TOP_CSR_BASE + 0x3C8)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_179_REG (CSR_ESCH_TOP_CSR_BASE + 0x3CC)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_180_REG (CSR_ESCH_TOP_CSR_BASE + 0x3D0)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_181_REG (CSR_ESCH_TOP_CSR_BASE + 0x3D4)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_182_REG (CSR_ESCH_TOP_CSR_BASE + 0x3D8)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_183_REG (CSR_ESCH_TOP_CSR_BASE + 0x3DC)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_184_REG (CSR_ESCH_TOP_CSR_BASE + 0x3E0)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_185_REG (CSR_ESCH_TOP_CSR_BASE + 0x3E4)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_186_REG (CSR_ESCH_TOP_CSR_BASE + 0x3E8)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_187_REG (CSR_ESCH_TOP_CSR_BASE + 0x3EC)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_188_REG (CSR_ESCH_TOP_CSR_BASE + 0x3F0)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_189_REG (CSR_ESCH_TOP_CSR_BASE + 0x3F4)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_190_REG (CSR_ESCH_TOP_CSR_BASE + 0x3F8)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_191_REG (CSR_ESCH_TOP_CSR_BASE + 0x3FC)  /* NETWORK LB Q SOURCE MAP */
#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_0_REG (CSR_ESCH_TOP_CSR_BASE + 0x400)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_1_REG (CSR_ESCH_TOP_CSR_BASE + 0x404)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_2_REG (CSR_ESCH_TOP_CSR_BASE + 0x408)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_3_REG (CSR_ESCH_TOP_CSR_BASE + 0x40C)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_4_REG (CSR_ESCH_TOP_CSR_BASE + 0x410)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_5_REG (CSR_ESCH_TOP_CSR_BASE + 0x414)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_6_REG (CSR_ESCH_TOP_CSR_BASE + 0x418)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_7_REG (CSR_ESCH_TOP_CSR_BASE + 0x41C)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_8_REG (CSR_ESCH_TOP_CSR_BASE + 0x420)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_9_REG (CSR_ESCH_TOP_CSR_BASE + 0x424)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_10_REG (CSR_ESCH_TOP_CSR_BASE + 0x428)    /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_11_REG (CSR_ESCH_TOP_CSR_BASE + 0x42C)    /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_12_REG (CSR_ESCH_TOP_CSR_BASE + 0x430)    /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_13_REG (CSR_ESCH_TOP_CSR_BASE + 0x434)    /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_14_REG (CSR_ESCH_TOP_CSR_BASE + 0x438)    /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_15_REG (CSR_ESCH_TOP_CSR_BASE + 0x43C)    /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_16_REG (CSR_ESCH_TOP_CSR_BASE + 0x440)    /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_17_REG (CSR_ESCH_TOP_CSR_BASE + 0x444)    /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_18_REG (CSR_ESCH_TOP_CSR_BASE + 0x448)    /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_19_REG (CSR_ESCH_TOP_CSR_BASE + 0x44C)    /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_20_REG (CSR_ESCH_TOP_CSR_BASE + 0x450)    /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_21_REG (CSR_ESCH_TOP_CSR_BASE + 0x454)    /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_22_REG (CSR_ESCH_TOP_CSR_BASE + 0x458)    /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_23_REG (CSR_ESCH_TOP_CSR_BASE + 0x45C)    /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_24_REG (CSR_ESCH_TOP_CSR_BASE + 0x460)    /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_25_REG (CSR_ESCH_TOP_CSR_BASE + 0x464)    /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_26_REG (CSR_ESCH_TOP_CSR_BASE + 0x468)    /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_27_REG (CSR_ESCH_TOP_CSR_BASE + 0x46C)    /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_28_REG (CSR_ESCH_TOP_CSR_BASE + 0x470)    /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_29_REG (CSR_ESCH_TOP_CSR_BASE + 0x474)    /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_30_REG (CSR_ESCH_TOP_CSR_BASE + 0x478)    /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_31_REG (CSR_ESCH_TOP_CSR_BASE + 0x47C)    /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_32_REG (CSR_ESCH_TOP_CSR_BASE + 0x480)    /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_0_REG (CSR_ESCH_TOP_CSR_BASE + 0x500)   /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_1_REG (CSR_ESCH_TOP_CSR_BASE + 0x504)   /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_2_REG (CSR_ESCH_TOP_CSR_BASE + 0x508)   /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_3_REG (CSR_ESCH_TOP_CSR_BASE + 0x50C)   /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_4_REG (CSR_ESCH_TOP_CSR_BASE + 0x510)   /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_5_REG (CSR_ESCH_TOP_CSR_BASE + 0x514)   /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_6_REG (CSR_ESCH_TOP_CSR_BASE + 0x518)   /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_7_REG (CSR_ESCH_TOP_CSR_BASE + 0x51C)   /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_8_REG (CSR_ESCH_TOP_CSR_BASE + 0x520)   /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_9_REG (CSR_ESCH_TOP_CSR_BASE + 0x524)   /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_10_REG (CSR_ESCH_TOP_CSR_BASE + 0x528)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_11_REG (CSR_ESCH_TOP_CSR_BASE + 0x52C)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_12_REG (CSR_ESCH_TOP_CSR_BASE + 0x530)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_13_REG (CSR_ESCH_TOP_CSR_BASE + 0x534)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_14_REG (CSR_ESCH_TOP_CSR_BASE + 0x538)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_15_REG (CSR_ESCH_TOP_CSR_BASE + 0x53C)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_16_REG (CSR_ESCH_TOP_CSR_BASE + 0x540)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_17_REG (CSR_ESCH_TOP_CSR_BASE + 0x544)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_18_REG (CSR_ESCH_TOP_CSR_BASE + 0x548)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_19_REG (CSR_ESCH_TOP_CSR_BASE + 0x54C)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_20_REG (CSR_ESCH_TOP_CSR_BASE + 0x550)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_21_REG (CSR_ESCH_TOP_CSR_BASE + 0x554)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_22_REG (CSR_ESCH_TOP_CSR_BASE + 0x558)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_23_REG (CSR_ESCH_TOP_CSR_BASE + 0x55C)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_24_REG (CSR_ESCH_TOP_CSR_BASE + 0x560)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_25_REG (CSR_ESCH_TOP_CSR_BASE + 0x564)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_26_REG (CSR_ESCH_TOP_CSR_BASE + 0x568)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_27_REG (CSR_ESCH_TOP_CSR_BASE + 0x56C)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_28_REG (CSR_ESCH_TOP_CSR_BASE + 0x570)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_29_REG (CSR_ESCH_TOP_CSR_BASE + 0x574)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_30_REG (CSR_ESCH_TOP_CSR_BASE + 0x578)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_31_REG (CSR_ESCH_TOP_CSR_BASE + 0x57C)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_32_REG (CSR_ESCH_TOP_CSR_BASE + 0x580)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_33_REG (CSR_ESCH_TOP_CSR_BASE + 0x584)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_34_REG (CSR_ESCH_TOP_CSR_BASE + 0x588)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_35_REG (CSR_ESCH_TOP_CSR_BASE + 0x58C)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_36_REG (CSR_ESCH_TOP_CSR_BASE + 0x590)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_37_REG (CSR_ESCH_TOP_CSR_BASE + 0x594)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_38_REG (CSR_ESCH_TOP_CSR_BASE + 0x598)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_39_REG (CSR_ESCH_TOP_CSR_BASE + 0x59C)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_40_REG (CSR_ESCH_TOP_CSR_BASE + 0x5A0)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_41_REG (CSR_ESCH_TOP_CSR_BASE + 0x5A4)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_42_REG (CSR_ESCH_TOP_CSR_BASE + 0x5A8)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_43_REG (CSR_ESCH_TOP_CSR_BASE + 0x5AC)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_44_REG (CSR_ESCH_TOP_CSR_BASE + 0x5B0)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_45_REG (CSR_ESCH_TOP_CSR_BASE + 0x5B4)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_46_REG (CSR_ESCH_TOP_CSR_BASE + 0x5B8)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_47_REG (CSR_ESCH_TOP_CSR_BASE + 0x5BC)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_48_REG (CSR_ESCH_TOP_CSR_BASE + 0x5C0)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_49_REG (CSR_ESCH_TOP_CSR_BASE + 0x5C4)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_50_REG (CSR_ESCH_TOP_CSR_BASE + 0x5C8)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_51_REG (CSR_ESCH_TOP_CSR_BASE + 0x5CC)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_52_REG (CSR_ESCH_TOP_CSR_BASE + 0x5D0)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_53_REG (CSR_ESCH_TOP_CSR_BASE + 0x5D4)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_54_REG (CSR_ESCH_TOP_CSR_BASE + 0x5D8)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_55_REG (CSR_ESCH_TOP_CSR_BASE + 0x5DC)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_56_REG (CSR_ESCH_TOP_CSR_BASE + 0x5E0)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_57_REG (CSR_ESCH_TOP_CSR_BASE + 0x5E4)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_58_REG (CSR_ESCH_TOP_CSR_BASE + 0x5E8)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_59_REG (CSR_ESCH_TOP_CSR_BASE + 0x5EC)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_60_REG (CSR_ESCH_TOP_CSR_BASE + 0x5F0)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_61_REG (CSR_ESCH_TOP_CSR_BASE + 0x5F4)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_62_REG (CSR_ESCH_TOP_CSR_BASE + 0x5F8)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_63_REG (CSR_ESCH_TOP_CSR_BASE + 0x5FC)  /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_0_REG (CSR_ESCH_TOP_CSR_BASE + 0x600)      /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_1_REG (CSR_ESCH_TOP_CSR_BASE + 0x604)      /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_2_REG (CSR_ESCH_TOP_CSR_BASE + 0x608)      /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_3_REG (CSR_ESCH_TOP_CSR_BASE + 0x60C)      /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_4_REG (CSR_ESCH_TOP_CSR_BASE + 0x610)      /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_5_REG (CSR_ESCH_TOP_CSR_BASE + 0x614)      /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_6_REG (CSR_ESCH_TOP_CSR_BASE + 0x618)      /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_7_REG (CSR_ESCH_TOP_CSR_BASE + 0x61C)      /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_8_REG (CSR_ESCH_TOP_CSR_BASE + 0x620)      /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_9_REG (CSR_ESCH_TOP_CSR_BASE + 0x624)      /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_10_REG (CSR_ESCH_TOP_CSR_BASE + 0x628)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_11_REG (CSR_ESCH_TOP_CSR_BASE + 0x62C)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_12_REG (CSR_ESCH_TOP_CSR_BASE + 0x630)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_13_REG (CSR_ESCH_TOP_CSR_BASE + 0x634)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_14_REG (CSR_ESCH_TOP_CSR_BASE + 0x638)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_15_REG (CSR_ESCH_TOP_CSR_BASE + 0x63C)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_16_REG (CSR_ESCH_TOP_CSR_BASE + 0x640)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_17_REG (CSR_ESCH_TOP_CSR_BASE + 0x644)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_18_REG (CSR_ESCH_TOP_CSR_BASE + 0x648)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_19_REG (CSR_ESCH_TOP_CSR_BASE + 0x64C)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_20_REG (CSR_ESCH_TOP_CSR_BASE + 0x650)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_21_REG (CSR_ESCH_TOP_CSR_BASE + 0x654)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_22_REG (CSR_ESCH_TOP_CSR_BASE + 0x658)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_23_REG (CSR_ESCH_TOP_CSR_BASE + 0x65C)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_24_REG (CSR_ESCH_TOP_CSR_BASE + 0x660)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_25_REG (CSR_ESCH_TOP_CSR_BASE + 0x664)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_26_REG (CSR_ESCH_TOP_CSR_BASE + 0x668)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_27_REG (CSR_ESCH_TOP_CSR_BASE + 0x66C)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_28_REG (CSR_ESCH_TOP_CSR_BASE + 0x670)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_29_REG (CSR_ESCH_TOP_CSR_BASE + 0x674)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_30_REG (CSR_ESCH_TOP_CSR_BASE + 0x678)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_31_REG (CSR_ESCH_TOP_CSR_BASE + 0x67C)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_32_REG (CSR_ESCH_TOP_CSR_BASE + 0x680)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_33_REG (CSR_ESCH_TOP_CSR_BASE + 0x684)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_34_REG (CSR_ESCH_TOP_CSR_BASE + 0x688)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_35_REG (CSR_ESCH_TOP_CSR_BASE + 0x68C)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_36_REG (CSR_ESCH_TOP_CSR_BASE + 0x690)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_37_REG (CSR_ESCH_TOP_CSR_BASE + 0x694)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_38_REG (CSR_ESCH_TOP_CSR_BASE + 0x698)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_39_REG (CSR_ESCH_TOP_CSR_BASE + 0x69C)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_40_REG (CSR_ESCH_TOP_CSR_BASE + 0x6A0)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_41_REG (CSR_ESCH_TOP_CSR_BASE + 0x6A4)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_42_REG (CSR_ESCH_TOP_CSR_BASE + 0x6A8)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_43_REG (CSR_ESCH_TOP_CSR_BASE + 0x6AC)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_44_REG (CSR_ESCH_TOP_CSR_BASE + 0x6B0)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_45_REG (CSR_ESCH_TOP_CSR_BASE + 0x6B4)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_46_REG (CSR_ESCH_TOP_CSR_BASE + 0x6B8)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_47_REG (CSR_ESCH_TOP_CSR_BASE + 0x6BC)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_48_REG (CSR_ESCH_TOP_CSR_BASE + 0x6C0)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_49_REG (CSR_ESCH_TOP_CSR_BASE + 0x6C4)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_50_REG (CSR_ESCH_TOP_CSR_BASE + 0x6C8)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_51_REG (CSR_ESCH_TOP_CSR_BASE + 0x6CC)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_52_REG (CSR_ESCH_TOP_CSR_BASE + 0x6D0)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_53_REG (CSR_ESCH_TOP_CSR_BASE + 0x6D4)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_54_REG (CSR_ESCH_TOP_CSR_BASE + 0x6D8)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_55_REG (CSR_ESCH_TOP_CSR_BASE + 0x6DC)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_56_REG (CSR_ESCH_TOP_CSR_BASE + 0x6E0)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_57_REG (CSR_ESCH_TOP_CSR_BASE + 0x6E4)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_58_REG (CSR_ESCH_TOP_CSR_BASE + 0x6E8)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_59_REG (CSR_ESCH_TOP_CSR_BASE + 0x6EC)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_60_REG (CSR_ESCH_TOP_CSR_BASE + 0x6F0)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_61_REG (CSR_ESCH_TOP_CSR_BASE + 0x6F4)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_62_REG (CSR_ESCH_TOP_CSR_BASE + 0x6F8)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_63_REG (CSR_ESCH_TOP_CSR_BASE + 0x6FC)     /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NETLB_FIFO_TH_0_REG (CSR_ESCH_TOP_CSR_BASE + 0x700)    /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NETLB_FIFO_TH_1_REG (CSR_ESCH_TOP_CSR_BASE + 0x704)    /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_NETLB_FIFO_TH_2_REG (CSR_ESCH_TOP_CSR_BASE + 0x708)    /* 信用反压阈值配置 */
#define CSR_ESCH_TOP_CSR_ESCH_MEM_CTRL_REG (CSR_ESCH_TOP_CSR_BASE + 0x750)           /* MEM 配置 */
#define CSR_ESCH_TOP_CSR_ESCH_MEM_ERR_REQ0_REG (CSR_ESCH_TOP_CSR_BASE + 0x754)       /* MEM 配置 */
#define CSR_ESCH_TOP_CSR_ESCH_MEM_ERR_REQ1_REG (CSR_ESCH_TOP_CSR_BASE + 0x758)       /* MEM 配置 */
#define CSR_ESCH_TOP_CSR_ESCH_INT_VECTOR_REG (CSR_ESCH_TOP_CSR_BASE + 0x760)         /* 中断向量 */
#define CSR_ESCH_TOP_CSR_ESCH_INT_REG (CSR_ESCH_TOP_CSR_BASE + 0x764)                /* 中断状态 */
#define CSR_ESCH_TOP_CSR_ESCH_INT_EN_REG (CSR_ESCH_TOP_CSR_BASE + 0x768)             /* 中断屏蔽 */
#define CSR_ESCH_TOP_CSR_ESCH_INT0_STICKY0_REG (CSR_ESCH_TOP_CSR_BASE + 0x76C)       /* 中断0的sticky信息 */
#define CSR_ESCH_TOP_CSR_ESCH_INT0_STICKY1_REG (CSR_ESCH_TOP_CSR_BASE + 0x770)       /* 中断1的sticky信息 */
#define CSR_ESCH_TOP_CSR_ESCH_INT0_STICKY2_REG (CSR_ESCH_TOP_CSR_BASE + 0x774)       /* 中断2的sticky信息 */
#define CSR_ESCH_TOP_CSR_ESCH_FCNP_CFG_REG (CSR_ESCH_TOP_CSR_BASE + 0x778)           /* FCNPshaper固定桶深配置 */
#define CSR_ESCH_TOP_CSR_ESCH_CPB_CH_CDT_CFG_REG (CSR_ESCH_TOP_CSR_BASE + 0x77C)     /* 信用深度统计 */
#define CSR_ESCH_TOP_CSR_ESCH_HPS_NML_COS_BP_REG (CSR_ESCH_TOP_CSR_BASE + 0x780)     /* 信用反压 */
#define CSR_ESCH_TOP_CSR_ESCH_HPS_UP_BP_REG (CSR_ESCH_TOP_CSR_BASE + 0x784)          /* 信用反压 */
#define CSR_ESCH_TOP_CSR_ESCH_HPS_LB_COS_HIGH_BP_REG (CSR_ESCH_TOP_CSR_BASE + 0x788) /* 信用反压 */
#define CSR_ESCH_TOP_CSR_ESCH_HPS_LB_COS_LOW_BP_REG (CSR_ESCH_TOP_CSR_BASE + 0x78C)  /* 信用反压 */
#define CSR_ESCH_TOP_CSR_ESCH_EPS_COS_HIGH_BP_REG (CSR_ESCH_TOP_CSR_BASE + 0x790)    /* 信用反压 */
#define CSR_ESCH_TOP_CSR_ESCH_EPS_COS_LOW_BP_REG (CSR_ESCH_TOP_CSR_BASE + 0x794)     /* 信用反压 */
#define CSR_ESCH_TOP_CSR_ESCH_EPS_LB_TYPE_BP_REG (CSR_ESCH_TOP_CSR_BASE + 0x79C)     /* 信用反压 */
#define CSR_ESCH_TOP_CSR_ESCH_MAG_HIGH_COS_BP_REG (CSR_ESCH_TOP_CSR_BASE + 0x7A0)    /* 信用反压 */
#define CSR_ESCH_TOP_CSR_ESCH_MAG_LOW_COS_BP_REG (CSR_ESCH_TOP_CSR_BASE + 0x7A4)     /* 信用反压 */

/* ESCH_EPS_CSR Base address of Module's Register */
#define CSR_ESCH_EPS_CSR_BASE (0xA800)

/* **************************************************************************** */
/*                      ESCH_EPS_CSR Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_ESCH_EPS_CSR_EPS_Q_INDRECT_CTRL_REG (CSR_ESCH_EPS_CSR_BASE + 0x0)          /* EPS 队列间接访问 */
#define CSR_ESCH_EPS_CSR_EPS_Q_INDRECT_TIMEOUT_REG (CSR_ESCH_EPS_CSR_BASE + 0x4)       /* EPS 队列间接访问 */
#define CSR_ESCH_EPS_CSR_EPS_Q_INDRECT_DATA_REG (CSR_ESCH_EPS_CSR_BASE + 0x8)          /* EPS 队列间接访问 */
#define CSR_ESCH_EPS_CSR_EPS_COS_INDRECT_CTRL_REG (CSR_ESCH_EPS_CSR_BASE + 0x10)       /* EPS COS间接访问 */
#define CSR_ESCH_EPS_CSR_EPS_COS_INDRECT_TIMEOUT_REG (CSR_ESCH_EPS_CSR_BASE + 0x14)    /* EPS COS间接访问 */
#define CSR_ESCH_EPS_CSR_EPS_COS_INDRECT_DATA_REG (CSR_ESCH_EPS_CSR_BASE + 0x18)       /* EPS COS间接访问 */
#define CSR_ESCH_EPS_CSR_EPS_TC_P_INDRECT_CTRL_REG (CSR_ESCH_EPS_CSR_BASE + 0x20)      /* EPS TC和Port间接访问 */
#define CSR_ESCH_EPS_CSR_EPS_TC_P_INDRECT_TIMEOUT_REG (CSR_ESCH_EPS_CSR_BASE + 0x24)   /* EPS TC和Port间接访问 */
#define CSR_ESCH_EPS_CSR_EPS_TC_P_INDRECT_DATA_REG (CSR_ESCH_EPS_CSR_BASE + 0x28)      /* EPS TC和Port间接访问 */
#define CSR_ESCH_EPS_CSR_EPS_LB_Q_INDRECT_CTRL_REG (CSR_ESCH_EPS_CSR_BASE + 0x30)      /* EPS LB 队列间接访问 */
#define CSR_ESCH_EPS_CSR_EPS_LB_Q_INDRECT_TIMEOUT_REG (CSR_ESCH_EPS_CSR_BASE + 0x34)   /* EPS LB 队列间接访问 */
#define CSR_ESCH_EPS_CSR_EPS_LB_Q_INDRECT_DATA_REG (CSR_ESCH_EPS_CSR_BASE + 0x38)      /* EPS LB 队列间接访问 */
#define CSR_ESCH_EPS_CSR_EPS_LB_P_T_INDRECT_CTRL_REG (CSR_ESCH_EPS_CSR_BASE + 0x40)    /* EPS LB Port和Type间接访问 */
#define CSR_ESCH_EPS_CSR_EPS_LB_P_T_INDRECT_TIMEOUT_REG (CSR_ESCH_EPS_CSR_BASE + 0x44) /* EPS LB Port和Type间接访问 */
#define CSR_ESCH_EPS_CSR_EPS_LB_P_T_INDRECT_DATA_REG (CSR_ESCH_EPS_CSR_BASE + 0x48)    /* EPS LB Port和Type间接访问 */
#define CSR_ESCH_EPS_CSR_EPS_P_SOFT_BP_CFG_REG (CSR_ESCH_EPS_CSR_BASE + 0x50)          /* EPS PORT节点软反压配置 */
#define CSR_ESCH_EPS_CSR_EPS_COS_BP_EN0_REG (CSR_ESCH_EPS_CSR_BASE + 0x54)        /* ETH端口队列反压响应使能寄存器0 */
#define CSR_ESCH_EPS_CSR_EPS_COS_BP_EN1_REG (CSR_ESCH_EPS_CSR_BASE + 0x58)        /* ETH端口队列反压响应使能寄存器1 */
#define CSR_ESCH_EPS_CSR_EPS_BP_MODE_REG (CSR_ESCH_EPS_CSR_BASE + 0x5C)           /* EPS BP 模式配置 register. */
#define CSR_ESCH_EPS_CSR_EPS_ROOT_CIR_CFG_REG (CSR_ESCH_EPS_CSR_BASE + 0x60)      /* EPS PORT GRP CIR shaper配置 */
#define CSR_ESCH_EPS_CSR_EPS_LB_ROOT_CIR_CFG_REG (CSR_ESCH_EPS_CSR_BASE + 0x64)   /* EPS LB PORT GRP CIR shaper配置 */
#define CSR_ESCH_EPS_CSR_EPS_ALL_CIR_CFG_REG (CSR_ESCH_EPS_CSR_BASE + 0x68)       /* EPS ALL CIR shaper配置 */
#define CSR_ESCH_EPS_CSR_EPS_ROOT_CIR_CNT_REG (CSR_ESCH_EPS_CSR_BASE + 0x6C)      /* EPS_ROOT_CIR_CNT */
#define CSR_ESCH_EPS_CSR_EPS_LB_ROOT_CIR_CNT_REG (CSR_ESCH_EPS_CSR_BASE + 0x70)   /* EPS_LB_ROOT_CIR_CNT */
#define CSR_ESCH_EPS_CSR_EPS_ROOT_WGT_CFG_REG (CSR_ESCH_EPS_CSR_BASE + 0x78)      /* EPS_ROOT_WGT_CNT */
#define CSR_ESCH_EPS_CSR_EPS_NML_ROOT_WGT_CNT_REG (CSR_ESCH_EPS_CSR_BASE + 0x80)  /* NML ROOT_WGT */
#define CSR_ESCH_EPS_CSR_EPS_LB_ROOT_WGT_CNT_REG (CSR_ESCH_EPS_CSR_BASE + 0x84)   /* LB_ROOT_WGT */
#define CSR_ESCH_EPS_CSR_EPS_ECC_1BIT_ERR_CNT_REG (CSR_ESCH_EPS_CSR_BASE + 0x100) /* EPS 1bit ECC错误计数统计 */
#define CSR_ESCH_EPS_CSR_EPS_ECC_2BIT_ERR_CNT_REG (CSR_ESCH_EPS_CSR_BASE + 0x104) /* EPS 2bit ECC错误计数统计 */
#define CSR_ESCH_EPS_CSR_EPS_DQS_CNT_REG (CSR_ESCH_EPS_CSR_BASE + 0x108)          /* 出队次数统计 */
#define CSR_ESCH_EPS_CSR_EPS_EQS_CNT_REG (CSR_ESCH_EPS_CSR_BASE + 0x10C)          /* 入队次数统计 */
#define CSR_ESCH_EPS_CSR_EPS_FIFO_CNT_REG (CSR_ESCH_EPS_CSR_BASE + 0x110)         /* EPS FIFO当前深度 */
#define CSR_ESCH_EPS_CSR_EPS_INNER_ERR_ST_REG (CSR_ESCH_EPS_CSR_BASE + 0x114)     /* EPS 内部错误状态 */

/* ESCH_HPS_CSR Base address of Module's Register */
#define CSR_ESCH_HPS_CSR_BASE (0xA000)

/* **************************************************************************** */
/*                      ESCH_HPS_CSR Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_ESCH_HPS_CSR_HPS_INDRECT_CTRL_REG (CSR_ESCH_HPS_CSR_BASE + 0x0)    /* 间接访问寄存器 */
#define CSR_ESCH_HPS_CSR_HPS_INDRECT_TIMEOUT_REG (CSR_ESCH_HPS_CSR_BASE + 0x4) /* 间接访问寄存器 */
#define CSR_ESCH_HPS_CSR_HPS_INDRECT_DATA_REG (CSR_ESCH_HPS_CSR_BASE + 0x8)    /* 间接访问寄存器 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_CPPI_SHAP_TYPE_CFG_REG \
    (CSR_ESCH_HPS_CSR_BASE + 0x14) /* HPS CPPI PORT SHAPER整形类型配置寄存器 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_SOFT_BP_CFG_REG (CSR_ESCH_HPS_CSR_BASE + 0x18) /* HPS PORT节点软反压配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_ROOT_SHAP_TYPE_CFG_REG \
    (CSR_ESCH_HPS_CSR_BASE + 0x1C) /* HPS CPPI PORT SHAPER整形类型配置寄存器 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_UPQ_SHAP_TYPE_CFG_REG \
    (CSR_ESCH_HPS_CSR_BASE + 0x60) /* HPS UP QUEUE SHAPER整形类型配置寄存器 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_ALL_ROOT_WGT_CFG_REG (CSR_ESCH_HPS_CSR_BASE + 0x100)  /* ROOT DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_ROOT_CIR_CFG_REG (CSR_ESCH_HPS_CSR_BASE + 0x104)      /* Normal RootCIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_ROOT_CIR_CFG_REG (CSR_ESCH_HPS_CSR_BASE + 0x108)   /* loopback RootCIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CFG_0_REG (CSR_ESCH_HPS_CSR_BASE + 0x110)    /* LB Port DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CFG_1_REG (CSR_ESCH_HPS_CSR_BASE + 0x114)    /* LB Port DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CFG_2_REG (CSR_ESCH_HPS_CSR_BASE + 0x118)    /* LB Port DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CFG_3_REG (CSR_ESCH_HPS_CSR_BASE + 0x11C)    /* LB Port DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CFG_4_REG (CSR_ESCH_HPS_CSR_BASE + 0x120)    /* LB Port DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CFG_5_REG (CSR_ESCH_HPS_CSR_BASE + 0x124)    /* LB Port DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CFG_6_REG (CSR_ESCH_HPS_CSR_BASE + 0x128)    /* LB Port DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CFG_7_REG (CSR_ESCH_HPS_CSR_BASE + 0x12C)    /* LB Port DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_CFG_0_REG (CSR_ESCH_HPS_CSR_BASE + 0x130)    /* LB Port CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_CFG_1_REG (CSR_ESCH_HPS_CSR_BASE + 0x134)    /* LB Port CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_CFG_2_REG (CSR_ESCH_HPS_CSR_BASE + 0x138)    /* LB Port CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_CFG_3_REG (CSR_ESCH_HPS_CSR_BASE + 0x13C)    /* LB Port CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_CFG_4_REG (CSR_ESCH_HPS_CSR_BASE + 0x140)    /* LB Port CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_CFG_5_REG (CSR_ESCH_HPS_CSR_BASE + 0x144)    /* LB Port CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_CFG_6_REG (CSR_ESCH_HPS_CSR_BASE + 0x148)    /* LB Port CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_CFG_7_REG (CSR_ESCH_HPS_CSR_BASE + 0x14C)    /* LB Port CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_0_REG (CSR_ESCH_HPS_CSR_BASE + 0x150)    /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_1_REG (CSR_ESCH_HPS_CSR_BASE + 0x154)    /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_2_REG (CSR_ESCH_HPS_CSR_BASE + 0x158)    /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_3_REG (CSR_ESCH_HPS_CSR_BASE + 0x15C)    /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_4_REG (CSR_ESCH_HPS_CSR_BASE + 0x160)    /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_5_REG (CSR_ESCH_HPS_CSR_BASE + 0x164)    /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_6_REG (CSR_ESCH_HPS_CSR_BASE + 0x168)    /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_7_REG (CSR_ESCH_HPS_CSR_BASE + 0x16C)    /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_8_REG (CSR_ESCH_HPS_CSR_BASE + 0x170)    /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_9_REG (CSR_ESCH_HPS_CSR_BASE + 0x174)    /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_10_REG (CSR_ESCH_HPS_CSR_BASE + 0x178)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_11_REG (CSR_ESCH_HPS_CSR_BASE + 0x17C)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_12_REG (CSR_ESCH_HPS_CSR_BASE + 0x180)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_13_REG (CSR_ESCH_HPS_CSR_BASE + 0x184)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_14_REG (CSR_ESCH_HPS_CSR_BASE + 0x188)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_15_REG (CSR_ESCH_HPS_CSR_BASE + 0x18C)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_16_REG (CSR_ESCH_HPS_CSR_BASE + 0x190)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_17_REG (CSR_ESCH_HPS_CSR_BASE + 0x194)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_18_REG (CSR_ESCH_HPS_CSR_BASE + 0x198)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_19_REG (CSR_ESCH_HPS_CSR_BASE + 0x19C)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_20_REG (CSR_ESCH_HPS_CSR_BASE + 0x1A0)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_21_REG (CSR_ESCH_HPS_CSR_BASE + 0x1A4)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_22_REG (CSR_ESCH_HPS_CSR_BASE + 0x1A8)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_23_REG (CSR_ESCH_HPS_CSR_BASE + 0x1AC)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_24_REG (CSR_ESCH_HPS_CSR_BASE + 0x1B0)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_25_REG (CSR_ESCH_HPS_CSR_BASE + 0x1B4)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_26_REG (CSR_ESCH_HPS_CSR_BASE + 0x1B8)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_27_REG (CSR_ESCH_HPS_CSR_BASE + 0x1BC)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_28_REG (CSR_ESCH_HPS_CSR_BASE + 0x1C0)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_29_REG (CSR_ESCH_HPS_CSR_BASE + 0x1C4)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_30_REG (CSR_ESCH_HPS_CSR_BASE + 0x1C8)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_31_REG (CSR_ESCH_HPS_CSR_BASE + 0x1CC)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_32_REG (CSR_ESCH_HPS_CSR_BASE + 0x1D0)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_33_REG (CSR_ESCH_HPS_CSR_BASE + 0x1D4)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_34_REG (CSR_ESCH_HPS_CSR_BASE + 0x1D8)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_35_REG (CSR_ESCH_HPS_CSR_BASE + 0x1DC)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_36_REG (CSR_ESCH_HPS_CSR_BASE + 0x1E0)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_37_REG (CSR_ESCH_HPS_CSR_BASE + 0x1E4)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_38_REG (CSR_ESCH_HPS_CSR_BASE + 0x1E8)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_39_REG (CSR_ESCH_HPS_CSR_BASE + 0x1EC)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_40_REG (CSR_ESCH_HPS_CSR_BASE + 0x1F0)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_41_REG (CSR_ESCH_HPS_CSR_BASE + 0x1F4)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_42_REG (CSR_ESCH_HPS_CSR_BASE + 0x1F8)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_43_REG (CSR_ESCH_HPS_CSR_BASE + 0x1FC)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_44_REG (CSR_ESCH_HPS_CSR_BASE + 0x200)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_45_REG (CSR_ESCH_HPS_CSR_BASE + 0x204)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_46_REG (CSR_ESCH_HPS_CSR_BASE + 0x208)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_47_REG (CSR_ESCH_HPS_CSR_BASE + 0x20C)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_48_REG (CSR_ESCH_HPS_CSR_BASE + 0x210)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_49_REG (CSR_ESCH_HPS_CSR_BASE + 0x214)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_50_REG (CSR_ESCH_HPS_CSR_BASE + 0x218)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_51_REG (CSR_ESCH_HPS_CSR_BASE + 0x21C)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_52_REG (CSR_ESCH_HPS_CSR_BASE + 0x220)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_53_REG (CSR_ESCH_HPS_CSR_BASE + 0x224)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_54_REG (CSR_ESCH_HPS_CSR_BASE + 0x228)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_55_REG (CSR_ESCH_HPS_CSR_BASE + 0x22C)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_56_REG (CSR_ESCH_HPS_CSR_BASE + 0x230)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_57_REG (CSR_ESCH_HPS_CSR_BASE + 0x234)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_58_REG (CSR_ESCH_HPS_CSR_BASE + 0x238)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_59_REG (CSR_ESCH_HPS_CSR_BASE + 0x23C)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_60_REG (CSR_ESCH_HPS_CSR_BASE + 0x240)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_61_REG (CSR_ESCH_HPS_CSR_BASE + 0x244)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_62_REG (CSR_ESCH_HPS_CSR_BASE + 0x248)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_63_REG (CSR_ESCH_HPS_CSR_BASE + 0x24C)   /* LB Queue DWRR权重配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_0_REG (CSR_ESCH_HPS_CSR_BASE + 0x250)    /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_1_REG (CSR_ESCH_HPS_CSR_BASE + 0x254)    /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_2_REG (CSR_ESCH_HPS_CSR_BASE + 0x258)    /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_3_REG (CSR_ESCH_HPS_CSR_BASE + 0x25C)    /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_4_REG (CSR_ESCH_HPS_CSR_BASE + 0x260)    /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_5_REG (CSR_ESCH_HPS_CSR_BASE + 0x264)    /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_6_REG (CSR_ESCH_HPS_CSR_BASE + 0x268)    /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_7_REG (CSR_ESCH_HPS_CSR_BASE + 0x26C)    /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_8_REG (CSR_ESCH_HPS_CSR_BASE + 0x270)    /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_9_REG (CSR_ESCH_HPS_CSR_BASE + 0x274)    /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_10_REG (CSR_ESCH_HPS_CSR_BASE + 0x278)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_11_REG (CSR_ESCH_HPS_CSR_BASE + 0x27C)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_12_REG (CSR_ESCH_HPS_CSR_BASE + 0x280)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_13_REG (CSR_ESCH_HPS_CSR_BASE + 0x284)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_14_REG (CSR_ESCH_HPS_CSR_BASE + 0x288)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_15_REG (CSR_ESCH_HPS_CSR_BASE + 0x28C)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_16_REG (CSR_ESCH_HPS_CSR_BASE + 0x290)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_17_REG (CSR_ESCH_HPS_CSR_BASE + 0x294)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_18_REG (CSR_ESCH_HPS_CSR_BASE + 0x298)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_19_REG (CSR_ESCH_HPS_CSR_BASE + 0x29C)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_20_REG (CSR_ESCH_HPS_CSR_BASE + 0x2A0)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_21_REG (CSR_ESCH_HPS_CSR_BASE + 0x2A4)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_22_REG (CSR_ESCH_HPS_CSR_BASE + 0x2A8)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_23_REG (CSR_ESCH_HPS_CSR_BASE + 0x2AC)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_24_REG (CSR_ESCH_HPS_CSR_BASE + 0x2B0)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_25_REG (CSR_ESCH_HPS_CSR_BASE + 0x2B4)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_26_REG (CSR_ESCH_HPS_CSR_BASE + 0x2B8)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_27_REG (CSR_ESCH_HPS_CSR_BASE + 0x2BC)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_28_REG (CSR_ESCH_HPS_CSR_BASE + 0x2C0)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_29_REG (CSR_ESCH_HPS_CSR_BASE + 0x2C4)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_30_REG (CSR_ESCH_HPS_CSR_BASE + 0x2C8)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_31_REG (CSR_ESCH_HPS_CSR_BASE + 0x2CC)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_32_REG (CSR_ESCH_HPS_CSR_BASE + 0x2D0)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_33_REG (CSR_ESCH_HPS_CSR_BASE + 0x2D4)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_34_REG (CSR_ESCH_HPS_CSR_BASE + 0x2D8)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_35_REG (CSR_ESCH_HPS_CSR_BASE + 0x2DC)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_36_REG (CSR_ESCH_HPS_CSR_BASE + 0x2E0)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_37_REG (CSR_ESCH_HPS_CSR_BASE + 0x2E4)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_38_REG (CSR_ESCH_HPS_CSR_BASE + 0x2E8)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_39_REG (CSR_ESCH_HPS_CSR_BASE + 0x2EC)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_40_REG (CSR_ESCH_HPS_CSR_BASE + 0x2F0)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_41_REG (CSR_ESCH_HPS_CSR_BASE + 0x2F4)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_42_REG (CSR_ESCH_HPS_CSR_BASE + 0x2F8)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_43_REG (CSR_ESCH_HPS_CSR_BASE + 0x2FC)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_44_REG (CSR_ESCH_HPS_CSR_BASE + 0x300)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_45_REG (CSR_ESCH_HPS_CSR_BASE + 0x304)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_46_REG (CSR_ESCH_HPS_CSR_BASE + 0x308)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_47_REG (CSR_ESCH_HPS_CSR_BASE + 0x30C)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_48_REG (CSR_ESCH_HPS_CSR_BASE + 0x310)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_49_REG (CSR_ESCH_HPS_CSR_BASE + 0x314)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_50_REG (CSR_ESCH_HPS_CSR_BASE + 0x318)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_51_REG (CSR_ESCH_HPS_CSR_BASE + 0x31C)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_52_REG (CSR_ESCH_HPS_CSR_BASE + 0x320)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_53_REG (CSR_ESCH_HPS_CSR_BASE + 0x324)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_54_REG (CSR_ESCH_HPS_CSR_BASE + 0x328)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_55_REG (CSR_ESCH_HPS_CSR_BASE + 0x32C)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_56_REG (CSR_ESCH_HPS_CSR_BASE + 0x330)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_57_REG (CSR_ESCH_HPS_CSR_BASE + 0x334)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_58_REG (CSR_ESCH_HPS_CSR_BASE + 0x338)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_59_REG (CSR_ESCH_HPS_CSR_BASE + 0x33C)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_60_REG (CSR_ESCH_HPS_CSR_BASE + 0x340)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_61_REG (CSR_ESCH_HPS_CSR_BASE + 0x344)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_62_REG (CSR_ESCH_HPS_CSR_BASE + 0x348)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_63_REG (CSR_ESCH_HPS_CSR_BASE + 0x34C)   /* LB Queue CIR配置 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_ROOT_WGT_CNT_0_REG (CSR_ESCH_HPS_CSR_BASE + 0x400)    /* ROOT级 DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_ROOT_WGT_CNT_1_REG (CSR_ESCH_HPS_CSR_BASE + 0x404)    /* ROOT级 DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CNT_0_REG (CSR_ESCH_HPS_CSR_BASE + 0x410)    /* LB_P DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CNT_1_REG (CSR_ESCH_HPS_CSR_BASE + 0x414)    /* LB_P DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CNT_2_REG (CSR_ESCH_HPS_CSR_BASE + 0x418)    /* LB_P DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CNT_3_REG (CSR_ESCH_HPS_CSR_BASE + 0x41C)    /* LB_P DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CNT_4_REG (CSR_ESCH_HPS_CSR_BASE + 0x420)    /* LB_P DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CNT_5_REG (CSR_ESCH_HPS_CSR_BASE + 0x424)    /* LB_P DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CNT_6_REG (CSR_ESCH_HPS_CSR_BASE + 0x428)    /* LB_P DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CNT_7_REG (CSR_ESCH_HPS_CSR_BASE + 0x42C)    /* LB_P DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_0_REG (CSR_ESCH_HPS_CSR_BASE + 0x430)    /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_1_REG (CSR_ESCH_HPS_CSR_BASE + 0x434)    /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_2_REG (CSR_ESCH_HPS_CSR_BASE + 0x438)    /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_3_REG (CSR_ESCH_HPS_CSR_BASE + 0x43C)    /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_4_REG (CSR_ESCH_HPS_CSR_BASE + 0x440)    /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_5_REG (CSR_ESCH_HPS_CSR_BASE + 0x444)    /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_6_REG (CSR_ESCH_HPS_CSR_BASE + 0x448)    /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_7_REG (CSR_ESCH_HPS_CSR_BASE + 0x44C)    /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_8_REG (CSR_ESCH_HPS_CSR_BASE + 0x450)    /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_9_REG (CSR_ESCH_HPS_CSR_BASE + 0x454)    /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_10_REG (CSR_ESCH_HPS_CSR_BASE + 0x458)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_11_REG (CSR_ESCH_HPS_CSR_BASE + 0x45C)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_12_REG (CSR_ESCH_HPS_CSR_BASE + 0x460)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_13_REG (CSR_ESCH_HPS_CSR_BASE + 0x464)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_14_REG (CSR_ESCH_HPS_CSR_BASE + 0x468)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_15_REG (CSR_ESCH_HPS_CSR_BASE + 0x46C)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_16_REG (CSR_ESCH_HPS_CSR_BASE + 0x470)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_17_REG (CSR_ESCH_HPS_CSR_BASE + 0x474)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_18_REG (CSR_ESCH_HPS_CSR_BASE + 0x478)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_19_REG (CSR_ESCH_HPS_CSR_BASE + 0x47C)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_20_REG (CSR_ESCH_HPS_CSR_BASE + 0x480)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_21_REG (CSR_ESCH_HPS_CSR_BASE + 0x484)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_22_REG (CSR_ESCH_HPS_CSR_BASE + 0x488)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_23_REG (CSR_ESCH_HPS_CSR_BASE + 0x48C)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_24_REG (CSR_ESCH_HPS_CSR_BASE + 0x490)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_25_REG (CSR_ESCH_HPS_CSR_BASE + 0x494)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_26_REG (CSR_ESCH_HPS_CSR_BASE + 0x498)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_27_REG (CSR_ESCH_HPS_CSR_BASE + 0x49C)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_28_REG (CSR_ESCH_HPS_CSR_BASE + 0x4A0)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_29_REG (CSR_ESCH_HPS_CSR_BASE + 0x4A4)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_30_REG (CSR_ESCH_HPS_CSR_BASE + 0x4A8)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_31_REG (CSR_ESCH_HPS_CSR_BASE + 0x4AC)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_32_REG (CSR_ESCH_HPS_CSR_BASE + 0x4B0)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_33_REG (CSR_ESCH_HPS_CSR_BASE + 0x4B4)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_34_REG (CSR_ESCH_HPS_CSR_BASE + 0x4B8)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_35_REG (CSR_ESCH_HPS_CSR_BASE + 0x4BC)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_36_REG (CSR_ESCH_HPS_CSR_BASE + 0x4C0)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_37_REG (CSR_ESCH_HPS_CSR_BASE + 0x4C4)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_38_REG (CSR_ESCH_HPS_CSR_BASE + 0x4C8)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_39_REG (CSR_ESCH_HPS_CSR_BASE + 0x4CC)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_40_REG (CSR_ESCH_HPS_CSR_BASE + 0x4D0)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_41_REG (CSR_ESCH_HPS_CSR_BASE + 0x4D4)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_42_REG (CSR_ESCH_HPS_CSR_BASE + 0x4D8)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_43_REG (CSR_ESCH_HPS_CSR_BASE + 0x4DC)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_44_REG (CSR_ESCH_HPS_CSR_BASE + 0x4E0)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_45_REG (CSR_ESCH_HPS_CSR_BASE + 0x4E4)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_46_REG (CSR_ESCH_HPS_CSR_BASE + 0x4E8)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_47_REG (CSR_ESCH_HPS_CSR_BASE + 0x4EC)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_48_REG (CSR_ESCH_HPS_CSR_BASE + 0x4F0)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_49_REG (CSR_ESCH_HPS_CSR_BASE + 0x4F4)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_50_REG (CSR_ESCH_HPS_CSR_BASE + 0x4F8)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_51_REG (CSR_ESCH_HPS_CSR_BASE + 0x4FC)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_52_REG (CSR_ESCH_HPS_CSR_BASE + 0x500)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_53_REG (CSR_ESCH_HPS_CSR_BASE + 0x504)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_54_REG (CSR_ESCH_HPS_CSR_BASE + 0x508)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_55_REG (CSR_ESCH_HPS_CSR_BASE + 0x50C)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_56_REG (CSR_ESCH_HPS_CSR_BASE + 0x510)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_57_REG (CSR_ESCH_HPS_CSR_BASE + 0x514)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_58_REG (CSR_ESCH_HPS_CSR_BASE + 0x518)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_59_REG (CSR_ESCH_HPS_CSR_BASE + 0x51C)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_60_REG (CSR_ESCH_HPS_CSR_BASE + 0x520)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_61_REG (CSR_ESCH_HPS_CSR_BASE + 0x524)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_62_REG (CSR_ESCH_HPS_CSR_BASE + 0x528)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_63_REG (CSR_ESCH_HPS_CSR_BASE + 0x52C)   /* LB_Q DWRR WGT CNT */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_ROOT_CIR_TOKEN_0_REG (CSR_ESCH_HPS_CSR_BASE + 0x530)  /* ROOT CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_ROOT_CIR_TOKEN_1_REG (CSR_ESCH_HPS_CSR_BASE + 0x534)  /* ROOT CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_TOKEN_0_REG (CSR_ESCH_HPS_CSR_BASE + 0x540)  /* LB_P CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_TOKEN_1_REG (CSR_ESCH_HPS_CSR_BASE + 0x544)  /* LB_P CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_TOKEN_2_REG (CSR_ESCH_HPS_CSR_BASE + 0x548)  /* LB_P CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_TOKEN_3_REG (CSR_ESCH_HPS_CSR_BASE + 0x54C)  /* LB_P CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_TOKEN_4_REG (CSR_ESCH_HPS_CSR_BASE + 0x550)  /* LB_P CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_TOKEN_5_REG (CSR_ESCH_HPS_CSR_BASE + 0x554)  /* LB_P CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_TOKEN_6_REG (CSR_ESCH_HPS_CSR_BASE + 0x558)  /* LB_P CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_TOKEN_7_REG (CSR_ESCH_HPS_CSR_BASE + 0x55C)  /* LB_P CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_0_REG (CSR_ESCH_HPS_CSR_BASE + 0x560)  /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_1_REG (CSR_ESCH_HPS_CSR_BASE + 0x564)  /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_2_REG (CSR_ESCH_HPS_CSR_BASE + 0x568)  /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_3_REG (CSR_ESCH_HPS_CSR_BASE + 0x56C)  /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_4_REG (CSR_ESCH_HPS_CSR_BASE + 0x570)  /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_5_REG (CSR_ESCH_HPS_CSR_BASE + 0x574)  /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_6_REG (CSR_ESCH_HPS_CSR_BASE + 0x578)  /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_7_REG (CSR_ESCH_HPS_CSR_BASE + 0x57C)  /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_8_REG (CSR_ESCH_HPS_CSR_BASE + 0x580)  /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_9_REG (CSR_ESCH_HPS_CSR_BASE + 0x584)  /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_10_REG (CSR_ESCH_HPS_CSR_BASE + 0x588) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_11_REG (CSR_ESCH_HPS_CSR_BASE + 0x58C) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_12_REG (CSR_ESCH_HPS_CSR_BASE + 0x590) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_13_REG (CSR_ESCH_HPS_CSR_BASE + 0x594) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_14_REG (CSR_ESCH_HPS_CSR_BASE + 0x598) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_15_REG (CSR_ESCH_HPS_CSR_BASE + 0x59C) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_16_REG (CSR_ESCH_HPS_CSR_BASE + 0x5A0) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_17_REG (CSR_ESCH_HPS_CSR_BASE + 0x5A4) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_18_REG (CSR_ESCH_HPS_CSR_BASE + 0x5A8) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_19_REG (CSR_ESCH_HPS_CSR_BASE + 0x5AC) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_20_REG (CSR_ESCH_HPS_CSR_BASE + 0x5B0) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_21_REG (CSR_ESCH_HPS_CSR_BASE + 0x5B4) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_22_REG (CSR_ESCH_HPS_CSR_BASE + 0x5B8) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_23_REG (CSR_ESCH_HPS_CSR_BASE + 0x5BC) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_24_REG (CSR_ESCH_HPS_CSR_BASE + 0x5C0) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_25_REG (CSR_ESCH_HPS_CSR_BASE + 0x5C4) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_26_REG (CSR_ESCH_HPS_CSR_BASE + 0x5C8) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_27_REG (CSR_ESCH_HPS_CSR_BASE + 0x5CC) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_28_REG (CSR_ESCH_HPS_CSR_BASE + 0x5D0) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_29_REG (CSR_ESCH_HPS_CSR_BASE + 0x5D4) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_30_REG (CSR_ESCH_HPS_CSR_BASE + 0x5D8) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_31_REG (CSR_ESCH_HPS_CSR_BASE + 0x5DC) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_32_REG (CSR_ESCH_HPS_CSR_BASE + 0x5E0) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_33_REG (CSR_ESCH_HPS_CSR_BASE + 0x5E4) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_34_REG (CSR_ESCH_HPS_CSR_BASE + 0x5E8) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_35_REG (CSR_ESCH_HPS_CSR_BASE + 0x5EC) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_36_REG (CSR_ESCH_HPS_CSR_BASE + 0x5F0) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_37_REG (CSR_ESCH_HPS_CSR_BASE + 0x5F4) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_38_REG (CSR_ESCH_HPS_CSR_BASE + 0x5F8) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_39_REG (CSR_ESCH_HPS_CSR_BASE + 0x5FC) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_40_REG (CSR_ESCH_HPS_CSR_BASE + 0x600) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_41_REG (CSR_ESCH_HPS_CSR_BASE + 0x604) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_42_REG (CSR_ESCH_HPS_CSR_BASE + 0x608) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_43_REG (CSR_ESCH_HPS_CSR_BASE + 0x60C) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_44_REG (CSR_ESCH_HPS_CSR_BASE + 0x610) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_45_REG (CSR_ESCH_HPS_CSR_BASE + 0x614) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_46_REG (CSR_ESCH_HPS_CSR_BASE + 0x618) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_47_REG (CSR_ESCH_HPS_CSR_BASE + 0x61C) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_48_REG (CSR_ESCH_HPS_CSR_BASE + 0x620) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_49_REG (CSR_ESCH_HPS_CSR_BASE + 0x624) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_50_REG (CSR_ESCH_HPS_CSR_BASE + 0x628) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_51_REG (CSR_ESCH_HPS_CSR_BASE + 0x62C) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_52_REG (CSR_ESCH_HPS_CSR_BASE + 0x630) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_53_REG (CSR_ESCH_HPS_CSR_BASE + 0x634) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_54_REG (CSR_ESCH_HPS_CSR_BASE + 0x638) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_55_REG (CSR_ESCH_HPS_CSR_BASE + 0x63C) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_56_REG (CSR_ESCH_HPS_CSR_BASE + 0x640) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_57_REG (CSR_ESCH_HPS_CSR_BASE + 0x644) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_58_REG (CSR_ESCH_HPS_CSR_BASE + 0x648) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_59_REG (CSR_ESCH_HPS_CSR_BASE + 0x64C) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_60_REG (CSR_ESCH_HPS_CSR_BASE + 0x650) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_61_REG (CSR_ESCH_HPS_CSR_BASE + 0x654) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_62_REG (CSR_ESCH_HPS_CSR_BASE + 0x658) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_63_REG (CSR_ESCH_HPS_CSR_BASE + 0x65C) /* LB_Q CIR TOKEN数量 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_ECC_1BIT_ERR_CNT_REG (CSR_ESCH_HPS_CSR_BASE + 0x660)  /* HPS 1bit ECC错误计数统计 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_ECC_2BIT_ERR_CNT_REG (CSR_ESCH_HPS_CSR_BASE + 0x664)  /* HPS 2bit ECC错误计数统计 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_DQS_CNT_REG (CSR_ESCH_HPS_CSR_BASE + 0x668)           /* 出队次数统计 */
#define CSR_ESCH_HPS_CSR_ESCH_HPS_EQS_CNT_REG (CSR_ESCH_HPS_CSR_BASE + 0x66C)           /* 入队次数统计 */

#endif // ESCH_REG_OFFSET_H
